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Parallelism Increased Simulation Performance
February 16, 2010

Professor Sandeep Shukla.

Novel research on improving the simulation performance of hardware models has garnered a team led by Sandeep Shukla, Virginia Tech associate professor of electrical and computer engineering, and three of his students, a best paper award at the 15th Asia and South Pacific Design Automation Conference held recently in Taiwan.

The simulations are created in a language called SystemC, often used to shorten manufacturing design cycles and improve the time it takes to bring a product to the marketplace. Professor Shukla wrote the paper with Mahesh Nanjundappa and Bijoy A. Jose, his current Ph.D. students, and Hiren D. Patel, a former Ph.D. advisee.

Professor Shukla and his collaborators were able to speed up the simulation performance of certain SystemC-based hardware models by exploiting the high degree of parallelism afforded by today’s general purpose graphic processor units (GPGPU). Modern GPGPUs have multiple core processors capable of very high computation and data throughput. When parallelism is applied, the processors can run various parts of the simulations simultaneously, saving time.

Another aspect of their work was the use of a specific programming model called Compute Unified Device Architecture (CUDA). The CUDA execution model differs from the more commonly known central processing unit-based execution in terms of how the threads are scheduled. With CUDA, it is possible to have all of the threads execute simultaneously on separate processor cores and intermittently converge on the same path, thus increasing the efficiency.

Preliminary experiments showed they were able to speed up SystemC based simulations by factors of 30 to 100 times over previous performances.

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